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<div class="header">
  <div class="summary">
<a href="#groups">API Reference</a> &#124;
<a href="#nested-classes">Data Structures</a> &#124;
<a href="#define-members">Macros</a> &#124;
<a href="#typedef-members">Typedefs</a> &#124;
<a href="#enum-members">Enumerations</a> &#124;
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle"><div class="title">UART (Universal Asynchronous Receiver-Transmitter)<div class="ingroups"><a class="el" href="group__group__hal.html">HAL Drivers</a></div></div></div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p >High level interface for interacting with the Universal Asynchronous Receiver-Transmitter (UART). </p>
<p >The Universal Asynchronous Receiver/Transmitter (UART) protocol is an asynchronous serial interface protocol. UART communication is typically point-to-point. The UART interface consists of two signals:</p><ul>
<li>TX: Transmitter output</li>
<li>RX: Receiver input</li>
</ul>
<p >Additionally, two side-band signals are used to implement flow control in UART. Note that the flow control applies only to TX functionality.</p><ul>
<li>Clear to Send (CTS): This is an input signal to the transmitter. When active, it indicates that the slave is ready for the master to transmit data.</li>
<li>Ready to Send (RTS): This is an output signal from the receiver. When active, it indicates that the receiver is ready to receive data</li>
</ul>
<p >Flow control can be configured by providing cts / rts pins to <a class="el" href="group__group__hal__uart.html#ga99424544773e74b40ee678570aaedf51" title="Initialize the UART peripheral.">cyhal_uart_init()</a> and this will activate the feature in driver. In case flow control enablement status needs to be changed, <a class="el" href="group__group__hal__uart.html#gacd188597425e7bbf4536082277248e9f" title="Configure the UART for flow control.">cyhal_uart_enable_flow_control()</a> function can be used.</p>
<dl class="section note"><dt>Note</dt><dd>RTS flow control line is deasserted by the receiver when the number of bytes in the receiver RX FIFO reaches configured RTS RX FIFO level. RX FIFO on the receiver side could end up having an extra byte depending on if the transmitter has begun the transmission of the next byte when the RTS flow control line is deasserted by the receiver.</dd></dl>
<p>The data frame size, STOP bits and parity can be configured via <a class="el" href="group__group__hal__uart.html#structcyhal__uart__cfg__t">cyhal_uart_cfg_t</a>. The UART contains dedicated hardware buffers for transmit and receive. Optionally, either of these can be augmented with a software buffer. This is done in scope of <a class="el" href="group__group__hal__uart.html#ga99424544773e74b40ee678570aaedf51">cyhal_uart_init</a> (if appropriate configuration was selected) and <a class="el" href="group__group__hal__uart.html#ga76eddcf3f061a3984819bc8dfe503ae5">cyhal_uart_config_software_buffer</a> functions.</p>
<dl class="section note"><dt>Note</dt><dd>For applications that require printing messages on a UART terminal using printf(), the <a href="https://github.com/infineon/retarget-io">retarget-io</a> utility library can be used directly.</dd></dl>
<h1><a class="anchor" id="subsection_uart_features"></a>
Features</h1>
<ul>
<li>Configurable UART baud rate - <a class="el" href="group__group__hal__uart.html#ga14dcad3682e9b49e70b7f1e77cd862cc">cyhal_uart_set_baud</a></li>
<li>Configurable data frame size, STOP bits and parity - <a class="el" href="group__group__hal__uart.html#structcyhal__uart__cfg__t">cyhal_uart_cfg_t</a></li>
<li>Configurable interrupts and callback on UART events - <a class="el" href="group__group__hal__uart.html#gaf307283f3d358e4b6048846034df19aa">cyhal_uart_event_t</a> </li>
</ul>
<h1><a class="anchor" id="subsection_uart_interrupts"></a>
Interrupts and callbacks</h1>
<p >Interrupts are handled by callbacks based on events <a class="el" href="group__group__hal__uart.html#gaf307283f3d358e4b6048846034df19aa">cyhal_uart_event_t</a> If an event is disabled, the underlying interrupt is still enabled. Enabling or disabling an event only enables or disables the callback. </p><dl class="section note"><dt>Note</dt><dd>Care must be exercised when using the <a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa9b64ead890054ee5943b58bafc0f367e">CYHAL_UART_IRQ_RX_NOT_EMPTY</a> event. The callback must read all available received data or the interrupt will not be cleared leading to the callback being immediately retriggered. </dd></dl>
<h1><a class="anchor" id="subsection_uart_quickstart"></a>
Quick Start</h1>
<p ><a class="el" href="group__group__hal__uart.html#ga99424544773e74b40ee678570aaedf51">cyhal_uart_init</a> is used for UART initialization</p>
<h1><a class="anchor" id="subsection_uart_sample_snippets"></a>
Code Snippets</h1>
<h2><a class="anchor" id="subsection_uart_snippet_1"></a>
Snippet 1: Initialization and Configuration</h2>
<p >The following snippet initializes the UART block and assigns the <b>tx</b>, <b>rx</b> pins and sets the baudrate.</p>
<p >The snippet also shows how to use <a class="el" href="group__group__hal__uart.html#ga2be8141bcc5fcc349b0dce1c09c4e98f">cyhal_uart_write</a>, <a class="el" href="group__group__hal__uart.html#ga2184202b0b3995fcf625caf9f8c3dc05">cyhal_uart_putc</a>, <a class="el" href="group__group__hal__uart.html#gae436ac5108e3bc92f439c66c315e07ca">cyhal_uart_read</a> API.</p>
<div class="fragment"><div class="line"><span class="preprocessor">    #define DATA_BITS_8     8</span></div>
<div class="line"><span class="preprocessor">    #define STOP_BITS_1     1</span></div>
<div class="line"><span class="preprocessor">    #define BAUD_RATE       115200</span></div>
<div class="line"><span class="preprocessor">    #define UART_DELAY      10u</span></div>
<div class="line"><span class="preprocessor">    #define RX_BUF_SIZE     4</span></div>
<div class="line"><span class="preprocessor">    #define TX_BUF_SIZE     4</span></div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Variable Declarations</span></div>
<div class="line">    <a class="code hl_typedef" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>    rslt;</div>
<div class="line">    <a class="code hl_struct" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> uart_obj;</div>
<div class="line">    uint32_t     actualbaud;</div>
<div class="line">    uint8_t      tx_buf[TX_BUF_SIZE] = { <span class="charliteral">&#39;1&#39;</span>, <span class="charliteral">&#39;2&#39;</span>, <span class="charliteral">&#39;3&#39;</span>, <span class="charliteral">&#39;4&#39;</span> };</div>
<div class="line">    uint8_t      rx_buf[RX_BUF_SIZE];</div>
<div class="line">    <span class="keywordtype">size_t</span>       tx_length = TX_BUF_SIZE;</div>
<div class="line">    <span class="keywordtype">size_t</span>       rx_length = RX_BUF_SIZE;</div>
<div class="line">    uint32_t     value     = <span class="charliteral">&#39;A&#39;</span>;</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Initialize the UART configuration structure</span></div>
<div class="line">    <span class="keyword">const</span> <a class="code hl_struct" href="group__group__hal__uart.html#structcyhal__uart__cfg__t">cyhal_uart_cfg_t</a> uart_config =</div>
<div class="line">    {</div>
<div class="line">        .<a class="code hl_variable" href="group__group__hal__uart.html#a3360061aafad236eb9a9d347f9154643">data_bits</a>      = DATA_BITS_8,</div>
<div class="line">        .stop_bits      = STOP_BITS_1,</div>
<div class="line">        .parity         = <a class="code hl_enumvalue" href="group__group__hal__uart.html#gga410f06ac3fe5576220caf146fda6b77ba327098a8b49fceb10e330d561019d8cb">CYHAL_UART_PARITY_NONE</a>,</div>
<div class="line">        .rx_buffer      = rx_buf,</div>
<div class="line">        .rx_buffer_size = RX_BUF_SIZE</div>
<div class="line">    };</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Initialize the UART Block</span></div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__uart.html#ga99424544773e74b40ee678570aaedf51">cyhal_uart_init</a>(&amp;uart_obj, CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RX, <a class="code hl_enumvalue" href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#gga707195ce0627016bf371643bdd9caa51a3dbd1016ea99d087d747530418b89a01">NC</a>, <a class="code hl_enumvalue" href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#gga707195ce0627016bf371643bdd9caa51a3dbd1016ea99d087d747530418b89a01">NC</a>, NULL,</div>
<div class="line">                           &amp;uart_config);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Set the baud rate</span></div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__uart.html#ga14dcad3682e9b49e70b7f1e77cd862cc">cyhal_uart_set_baud</a>(&amp;uart_obj, BAUD_RATE, &amp;actualbaud);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Begin Tx Transfer</span></div>
<div class="line">    <a class="code hl_function" href="group__group__hal__uart.html#ga2be8141bcc5fcc349b0dce1c09c4e98f">cyhal_uart_write</a>(&amp;uart_obj, (<span class="keywordtype">void</span>*)tx_buf, &amp;tx_length);</div>
<div class="line">    <a class="code hl_function" href="group__group__hal__system.html#ga5f450769c1207d98134a9ced39adfdda">cyhal_system_delay_ms</a>(UART_DELAY);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Send a Character</span></div>
<div class="line">    <a class="code hl_function" href="group__group__hal__uart.html#ga2184202b0b3995fcf625caf9f8c3dc05">cyhal_uart_putc</a>(&amp;uart_obj, value);</div>
<div class="line">    <a class="code hl_function" href="group__group__hal__system.html#ga5f450769c1207d98134a9ced39adfdda">cyhal_system_delay_ms</a>(UART_DELAY);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Begin Rx Transfer</span></div>
<div class="line">    <a class="code hl_function" href="group__group__hal__uart.html#gae436ac5108e3bc92f439c66c315e07ca">cyhal_uart_read</a>(&amp;uart_obj, (<span class="keywordtype">void</span>*)rx_buf, &amp;rx_length);</div>
<div class="line">    <a class="code hl_function" href="group__group__hal__system.html#ga5f450769c1207d98134a9ced39adfdda">cyhal_system_delay_ms</a>(UART_DELAY);</div>
<div class="line"> </div>
<div class="ttc" id="agroup__group__hal__impl__hw__types_html_structcyhal__uart__t"><div class="ttname"><a href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a></div><div class="ttdoc">UART object.</div><div class="ttdef"><b>Definition:</b> cyhal_hw_types.h:1508</div></div>
<div class="ttc" id="agroup__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble_html_gga707195ce0627016bf371643bdd9caa51a3dbd1016ea99d087d747530418b89a01"><div class="ttname"><a href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#gga707195ce0627016bf371643bdd9caa51a3dbd1016ea99d087d747530418b89a01">NC</a></div><div class="ttdeci">@ NC</div><div class="ttdoc">No Connect/Invalid Pin.</div><div class="ttdef"><b>Definition:</b> cyhal_psoc6_01_104_m_csp_ble.h:53</div></div>
<div class="ttc" id="agroup__group__hal__system_html_ga5f450769c1207d98134a9ced39adfdda"><div class="ttname"><a href="group__group__hal__system.html#ga5f450769c1207d98134a9ced39adfdda">cyhal_system_delay_ms</a></div><div class="ttdeci">cy_rslt_t cyhal_system_delay_ms(uint32_t milliseconds)</div><div class="ttdoc">Requests that the current operation delays for at least the specified length of time.</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_a3360061aafad236eb9a9d347f9154643"><div class="ttname"><a href="group__group__hal__uart.html#a3360061aafad236eb9a9d347f9154643">cyhal_uart_cfg_t::data_bits</a></div><div class="ttdeci">uint32_t data_bits</div><div class="ttdoc">The number of data bits (generally 8 or 9)</div><div class="ttdef"><b>Definition:</b> cyhal_uart.h:202</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_ga14dcad3682e9b49e70b7f1e77cd862cc"><div class="ttname"><a href="group__group__hal__uart.html#ga14dcad3682e9b49e70b7f1e77cd862cc">cyhal_uart_set_baud</a></div><div class="ttdeci">cy_rslt_t cyhal_uart_set_baud(cyhal_uart_t *obj, uint32_t baudrate, uint32_t *actualbaud)</div><div class="ttdoc">Configure the baud rate.</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_ga2184202b0b3995fcf625caf9f8c3dc05"><div class="ttname"><a href="group__group__hal__uart.html#ga2184202b0b3995fcf625caf9f8c3dc05">cyhal_uart_putc</a></div><div class="ttdeci">cy_rslt_t cyhal_uart_putc(cyhal_uart_t *obj, uint32_t value)</div><div class="ttdoc">Send a character.</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_ga2be8141bcc5fcc349b0dce1c09c4e98f"><div class="ttname"><a href="group__group__hal__uart.html#ga2be8141bcc5fcc349b0dce1c09c4e98f">cyhal_uart_write</a></div><div class="ttdeci">cy_rslt_t cyhal_uart_write(cyhal_uart_t *obj, void *tx, size_t *tx_length)</div><div class="ttdoc">Begin synchronous TX transfer.</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_ga99424544773e74b40ee678570aaedf51"><div class="ttname"><a href="group__group__hal__uart.html#ga99424544773e74b40ee678570aaedf51">cyhal_uart_init</a></div><div class="ttdeci">cy_rslt_t cyhal_uart_init(cyhal_uart_t *obj, cyhal_gpio_t tx, cyhal_gpio_t rx, cyhal_gpio_t cts, cyhal_gpio_t rts, const cyhal_clock_t *clk, const cyhal_uart_cfg_t *cfg)</div><div class="ttdoc">Initialize the UART peripheral.</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_gae436ac5108e3bc92f439c66c315e07ca"><div class="ttname"><a href="group__group__hal__uart.html#gae436ac5108e3bc92f439c66c315e07ca">cyhal_uart_read</a></div><div class="ttdeci">cy_rslt_t cyhal_uart_read(cyhal_uart_t *obj, void *rx, size_t *rx_length)</div><div class="ttdoc">Begin synchronous RX transfer (enable interrupt for data collecting)</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_gga410f06ac3fe5576220caf146fda6b77ba327098a8b49fceb10e330d561019d8cb"><div class="ttname"><a href="group__group__hal__uart.html#gga410f06ac3fe5576220caf146fda6b77ba327098a8b49fceb10e330d561019d8cb">CYHAL_UART_PARITY_NONE</a></div><div class="ttdeci">@ CYHAL_UART_PARITY_NONE</div><div class="ttdoc">UART has no parity check</div><div class="ttdef"><b>Definition:</b> cyhal_uart.h:159</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_structcyhal__uart__cfg__t"><div class="ttname"><a href="group__group__hal__uart.html#structcyhal__uart__cfg__t">cyhal_uart_cfg_t</a></div><div class="ttdoc">Initial UART configuration.</div><div class="ttdef"><b>Definition:</b> cyhal_uart.h:201</div></div>
<div class="ttc" id="agroup__group__result_html_gaca79700fcc701534ce61778a9bcf57d1"><div class="ttname"><a href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a></div><div class="ttdeci">uint32_t cy_rslt_t</div><div class="ttdoc">Provides the result of an operation as a structured bitfield.</div><div class="ttdef"><b>Definition:</b> cy_result.h:438</div></div>
</div><!-- fragment --><h2><a class="anchor" id="subsection_uart_snippet_2"></a>
Snippet 2: Interrupts on UART events</h2>
<p >In the following snippet, UART events are handled in a callback function. The callback function has to be registered and then the events have to be enabled.</p>
<div class="fragment"><div class="line"><span class="comment">// Event handler callback function</span></div>
<div class="line"><span class="keywordtype">void</span> uart_event_handler(<span class="keywordtype">void</span>* handler_arg, <a class="code hl_enumeration" href="group__group__hal__uart.html#gaf307283f3d358e4b6048846034df19aa">cyhal_uart_event_t</a> event)</div>
<div class="line">{</div>
<div class="line">    (void)handler_arg;</div>
<div class="line"> </div>
<div class="line">    <span class="keywordflow">if</span> ((event &amp; <a class="code hl_enumvalue" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa9984c9f5e7f3b57c9740d390c35388db">CYHAL_UART_IRQ_TX_ERROR</a>) == <a class="code hl_enumvalue" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa9984c9f5e7f3b57c9740d390c35388db">CYHAL_UART_IRQ_TX_ERROR</a>)</div>
<div class="line">    {</div>
<div class="line">        <span class="comment">// An error occurred in Tx</span></div>
<div class="line">        <span class="comment">// Insert application code to handle Tx error</span></div>
<div class="line">    }</div>
<div class="line">    <span class="keywordflow">else</span> <span class="keywordflow">if</span> ((event &amp; <a class="code hl_enumvalue" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa656718b2b8343a46a64478b1d415bfc4">CYHAL_UART_IRQ_TX_DONE</a>) == <a class="code hl_enumvalue" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa656718b2b8343a46a64478b1d415bfc4">CYHAL_UART_IRQ_TX_DONE</a>)</div>
<div class="line">    {</div>
<div class="line">        <span class="comment">// All Tx data has been transmitted</span></div>
<div class="line">        <span class="comment">// Insert application code to handle Tx done</span></div>
<div class="line">    }</div>
<div class="line">    <span class="keywordflow">else</span> <span class="keywordflow">if</span> ((event &amp; <a class="code hl_enumvalue" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaac2db86894106691360ad64c35d33b578">CYHAL_UART_IRQ_RX_DONE</a>) == <a class="code hl_enumvalue" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaac2db86894106691360ad64c35d33b578">CYHAL_UART_IRQ_RX_DONE</a>)</div>
<div class="line">    {</div>
<div class="line">        <span class="comment">// All Rx data has been received</span></div>
<div class="line">        <span class="comment">// Insert application code to handle Rx done</span></div>
<div class="line">    }</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><a class="code hl_typedef" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> snippet_cyhal_uart_event()</div>
<div class="line">{</div>
<div class="line">    <span class="comment">// Macro Definitions</span></div>
<div class="line"><span class="preprocessor">    #define BAUD_RATE       115200</span></div>
<div class="line"><span class="preprocessor">    #define UART_DELAY      10u</span></div>
<div class="line"><span class="preprocessor">    #define TX_BUF_SIZE     4</span></div>
<div class="line"><span class="preprocessor">    #define INT_PRIORITY    3</span></div>
<div class="line"><span class="preprocessor">    #define DATA_BITS_8     8</span></div>
<div class="line"><span class="preprocessor">    #define STOP_BITS_1     1</span></div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Variable Declarations</span></div>
<div class="line">    <a class="code hl_typedef" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>    rslt;</div>
<div class="line">    <a class="code hl_struct" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> uart_obj;</div>
<div class="line">    uint8_t      tx_buf[TX_BUF_SIZE] = { <span class="charliteral">&#39;1&#39;</span>, <span class="charliteral">&#39;2&#39;</span>, <span class="charliteral">&#39;3&#39;</span>, <span class="charliteral">&#39;4&#39;</span> };</div>
<div class="line">    <span class="keywordtype">size_t</span>       tx_length           = TX_BUF_SIZE;</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Initialize the UART configuration structure</span></div>
<div class="line">    <span class="keyword">const</span> <a class="code hl_struct" href="group__group__hal__uart.html#structcyhal__uart__cfg__t">cyhal_uart_cfg_t</a> uart_config =</div>
<div class="line">    {</div>
<div class="line">        .<a class="code hl_variable" href="group__group__hal__uart.html#a3360061aafad236eb9a9d347f9154643">data_bits</a>      = DATA_BITS_8,</div>
<div class="line">        .stop_bits      = STOP_BITS_1,</div>
<div class="line">        .parity         = <a class="code hl_enumvalue" href="group__group__hal__uart.html#gga410f06ac3fe5576220caf146fda6b77ba327098a8b49fceb10e330d561019d8cb">CYHAL_UART_PARITY_NONE</a>,</div>
<div class="line">        .rx_buffer      = NULL,</div>
<div class="line">        .rx_buffer_size = 0</div>
<div class="line">    };</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Initialize the UART Block</span></div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__uart.html#ga99424544773e74b40ee678570aaedf51">cyhal_uart_init</a>(&amp;uart_obj, CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RX, <a class="code hl_enumvalue" href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#gga707195ce0627016bf371643bdd9caa51a3dbd1016ea99d087d747530418b89a01">NC</a>, <a class="code hl_enumvalue" href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#gga707195ce0627016bf371643bdd9caa51a3dbd1016ea99d087d747530418b89a01">NC</a>, NULL,</div>
<div class="line">                           &amp;uart_config);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// The UART callback handler registration</span></div>
<div class="line">    <span class="keywordflow">if</span> (<a class="code hl_define" href="group__group__result.html#gaf58fac450d9fff4472f03ad68f6e546e">CY_RSLT_SUCCESS</a> == rslt)</div>
<div class="line">    {</div>
<div class="line">        <a class="code hl_function" href="group__group__hal__uart.html#gae26bab64811713b1d69170352fe32c20">cyhal_uart_register_callback</a>(&amp;uart_obj, uart_event_handler, NULL);</div>
<div class="line"> </div>
<div class="line">        <span class="comment">// Enable required UART events</span></div>
<div class="line">        <a class="code hl_function" href="group__group__hal__uart.html#ga4dae4cef7dbf1d7935fe6dd6d31f282e">cyhal_uart_enable_event</a>(&amp;uart_obj,</div>
<div class="line">                                (<a class="code hl_enumeration" href="group__group__hal__uart.html#gaf307283f3d358e4b6048846034df19aa">cyhal_uart_event_t</a>)(<a class="code hl_enumvalue" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa656718b2b8343a46a64478b1d415bfc4">CYHAL_UART_IRQ_TX_DONE</a> |</div>
<div class="line">                                                     <a class="code hl_enumvalue" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa9984c9f5e7f3b57c9740d390c35388db">CYHAL_UART_IRQ_TX_ERROR</a> |</div>
<div class="line">                                                     <a class="code hl_enumvalue" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaac2db86894106691360ad64c35d33b578">CYHAL_UART_IRQ_RX_DONE</a>),</div>
<div class="line">                                INT_PRIORITY, <span class="keyword">true</span>);</div>
<div class="line"> </div>
<div class="line">        <span class="comment">// Begin asynchronous TX transfer</span></div>
<div class="line">        rslt = <a class="code hl_function" href="group__group__hal__uart.html#gab569e52660c519b775e3a15f3e2dbb46">cyhal_uart_write_async</a>(&amp;uart_obj, (<span class="keywordtype">void</span>*)tx_buf, tx_length);</div>
<div class="line">    }</div>
<div class="line"> </div>
<div class="line">    <span class="keywordflow">return</span> rslt;</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="preprocessor">#endif </span><span class="comment">/* !defined (SUT_WOUNDING_TEST) */</span><span class="preprocessor"></span></div>
<div class="line"> </div>
<div class="line"> </div>
<div class="ttc" id="agroup__group__hal__uart_html_ga4dae4cef7dbf1d7935fe6dd6d31f282e"><div class="ttname"><a href="group__group__hal__uart.html#ga4dae4cef7dbf1d7935fe6dd6d31f282e">cyhal_uart_enable_event</a></div><div class="ttdeci">void cyhal_uart_enable_event(cyhal_uart_t *obj, cyhal_uart_event_t event, uint8_t intr_priority, bool enable)</div><div class="ttdoc">Enable or disable specified UART events.</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_gab569e52660c519b775e3a15f3e2dbb46"><div class="ttname"><a href="group__group__hal__uart.html#gab569e52660c519b775e3a15f3e2dbb46">cyhal_uart_write_async</a></div><div class="ttdeci">cy_rslt_t cyhal_uart_write_async(cyhal_uart_t *obj, void *tx, size_t length)</div><div class="ttdoc">Begin asynchronous TX transfer.</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_gae26bab64811713b1d69170352fe32c20"><div class="ttname"><a href="group__group__hal__uart.html#gae26bab64811713b1d69170352fe32c20">cyhal_uart_register_callback</a></div><div class="ttdeci">void cyhal_uart_register_callback(cyhal_uart_t *obj, cyhal_uart_event_callback_t callback, void *callback_arg)</div><div class="ttdoc">Register a uart callback handler.</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_gaf307283f3d358e4b6048846034df19aa"><div class="ttname"><a href="group__group__hal__uart.html#gaf307283f3d358e4b6048846034df19aa">cyhal_uart_event_t</a></div><div class="ttdeci">cyhal_uart_event_t</div><div class="ttdoc">Enum to enable/disable/report interrupt cause flags.</div><div class="ttdef"><b>Definition:</b> cyhal_uart.h:166</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_ggaf307283f3d358e4b6048846034df19aaa656718b2b8343a46a64478b1d415bfc4"><div class="ttname"><a href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa656718b2b8343a46a64478b1d415bfc4">CYHAL_UART_IRQ_TX_DONE</a></div><div class="ttdeci">@ CYHAL_UART_IRQ_TX_DONE</div><div class="ttdoc">All TX data has been transmitted (applicable only for cyhal_uart_write_async)</div><div class="ttdef"><b>Definition:</b> cyhal_uart.h:169</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_ggaf307283f3d358e4b6048846034df19aaa9984c9f5e7f3b57c9740d390c35388db"><div class="ttname"><a href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa9984c9f5e7f3b57c9740d390c35388db">CYHAL_UART_IRQ_TX_ERROR</a></div><div class="ttdeci">@ CYHAL_UART_IRQ_TX_ERROR</div><div class="ttdoc">An error occurred during TX.</div><div class="ttdef"><b>Definition:</b> cyhal_uart.h:170</div></div>
<div class="ttc" id="agroup__group__hal__uart_html_ggaf307283f3d358e4b6048846034df19aaac2db86894106691360ad64c35d33b578"><div class="ttname"><a href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaac2db86894106691360ad64c35d33b578">CYHAL_UART_IRQ_RX_DONE</a></div><div class="ttdeci">@ CYHAL_UART_IRQ_RX_DONE</div><div class="ttdoc">All RX data has been received (applicable only for cyhal_uart_read_async)</div><div class="ttdef"><b>Definition:</b> cyhal_uart.h:172</div></div>
<div class="ttc" id="agroup__group__result_html_gaf58fac450d9fff4472f03ad68f6e546e"><div class="ttname"><a href="group__group__result.html#gaf58fac450d9fff4472f03ad68f6e546e">CY_RSLT_SUCCESS</a></div><div class="ttdeci">#define CY_RSLT_SUCCESS</div><div class="ttdoc">cy_rslt_t return value indicating success</div><div class="ttdef"><b>Definition:</b> cy_result.h:465</div></div>
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API Reference</h2></td></tr>
<tr class="memitem:group__group__hal__results__uart"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__results__uart.html">UART HAL Results</a></td></tr>
<tr class="memdesc:group__group__hal__results__uart"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART specific return codes. <br /></td></tr>
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Data Structures</h2></td></tr>
<tr class="memitem:structcyhal__uart__cfg__t"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#structcyhal__uart__cfg__t">cyhal_uart_cfg_t</a></td></tr>
<tr class="memdesc:structcyhal__uart__cfg__t"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initial UART configuration.  <a href="group__group__hal__uart.html#structcyhal__uart__cfg__t">More...</a><br /></td></tr>
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Macros</h2></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CYHAL_UART_DEFAULT_BAUD</b>&#160;&#160;&#160;115200</td></tr>
<tr class="memdesc:ga4b2c1534032adfc825026b5882fa2cd6"><td class="mdescLeft">&#160;</td><td class="mdescRight">The baud rate to set to if no clock is specified in the init function. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CYHAL_UART_MAX_BAUD_PERCENT_DIFFERENCE</b>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:ga9c1580a18947e5e976a997767b35b2c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">The maximum allowable difference between baud requested and actual baud. <br /></td></tr>
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Typedefs</h2></td></tr>
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typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><b>cyhal_uart_event_callback_t</b>) (void *callback_arg, <a class="el" href="group__group__hal__uart.html#gaf307283f3d358e4b6048846034df19aa">cyhal_uart_event_t</a> event)</td></tr>
<tr class="memdesc:gac444f4c849b289d99a75e0132f04fb65"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART callback function type. <br /></td></tr>
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Enumerations</h2></td></tr>
<tr class="memitem:ga410f06ac3fe5576220caf146fda6b77b"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga410f06ac3fe5576220caf146fda6b77b">cyhal_uart_parity_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#gga410f06ac3fe5576220caf146fda6b77ba327098a8b49fceb10e330d561019d8cb">CYHAL_UART_PARITY_NONE</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#gga410f06ac3fe5576220caf146fda6b77ba47c0ca4d5811d418e1bdaea54da62f7f">CYHAL_UART_PARITY_EVEN</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#gga410f06ac3fe5576220caf146fda6b77bad3844eeec5198449f882f5b3509282ea">CYHAL_UART_PARITY_ODD</a>
<br />
 }</td></tr>
<tr class="memdesc:ga410f06ac3fe5576220caf146fda6b77b"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART Parity.  <a href="group__group__hal__uart.html#ga410f06ac3fe5576220caf146fda6b77b">More...</a><br /></td></tr>
<tr class="separator:ga410f06ac3fe5576220caf146fda6b77b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf307283f3d358e4b6048846034df19aa"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#gaf307283f3d358e4b6048846034df19aa">cyhal_uart_event_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaadc15f333858441e62e2de2408a5ac767">CYHAL_UART_IRQ_NONE</a> = 0
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaaafb0642f2b2672db3ab4446e4c075864">CYHAL_UART_IRQ_TX_TRANSMIT_IN_FIFO</a> = 1 &lt;&lt; 1
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa656718b2b8343a46a64478b1d415bfc4">CYHAL_UART_IRQ_TX_DONE</a> = 1 &lt;&lt; 2
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa9984c9f5e7f3b57c9740d390c35388db">CYHAL_UART_IRQ_TX_ERROR</a> = 1 &lt;&lt; 3
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa7d073741825cc32b1be09fa59d6c8123">CYHAL_UART_IRQ_RX_FULL</a> = 1 &lt;&lt; 4
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaac2db86894106691360ad64c35d33b578">CYHAL_UART_IRQ_RX_DONE</a> = 1 &lt;&lt; 5
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa7f5d1f47a602c8ac0df06c121bf4ce46">CYHAL_UART_IRQ_RX_ERROR</a> = 1 &lt;&lt; 6
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa9b64ead890054ee5943b58bafc0f367e">CYHAL_UART_IRQ_RX_NOT_EMPTY</a> = 1 &lt;&lt; 7
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa0c7868cf2a2719db7fc2cb8c357e47a9">CYHAL_UART_IRQ_TX_EMPTY</a> = 1 &lt;&lt; 8
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaac116ebc0ab3ebc77dffd457f904ae029">CYHAL_UART_IRQ_TX_FIFO</a> = 1 &lt;&lt; 9
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaa1f0edecb2e607d340d868cdd997a16d3">CYHAL_UART_IRQ_RX_FIFO</a> = 1 &lt;&lt; 10
<br />
 }</td></tr>
<tr class="memdesc:gaf307283f3d358e4b6048846034df19aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enum to enable/disable/report interrupt cause flags.  <a href="group__group__hal__uart.html#gaf307283f3d358e4b6048846034df19aa">More...</a><br /></td></tr>
<tr class="separator:gaf307283f3d358e4b6048846034df19aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga17602199b64430d4b5503e14340c4ca0"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga17602199b64430d4b5503e14340c4ca0">cyhal_uart_fifo_type_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#gga17602199b64430d4b5503e14340c4ca0ae0cb3a0275909eb435e1d892dcc6703c">CYHAL_UART_FIFO_RX</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#gga17602199b64430d4b5503e14340c4ca0a2e87281f1bf6b951e55f23edc21e606e">CYHAL_UART_FIFO_TX</a>
<br />
 }</td></tr>
<tr class="memdesc:ga17602199b64430d4b5503e14340c4ca0"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART FIFO type.  <a href="group__group__hal__uart.html#ga17602199b64430d4b5503e14340c4ca0">More...</a><br /></td></tr>
<tr class="separator:ga17602199b64430d4b5503e14340c4ca0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga79c475fe87b88afece099da885605075"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga79c475fe87b88afece099da885605075">cyhal_uart_output_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#gga79c475fe87b88afece099da885605075a726f4bf351f0fd57da573087def9745c">CYHAL_UART_OUTPUT_TRIGGER_RX_FIFO_LEVEL_REACHED</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__uart.html#gga79c475fe87b88afece099da885605075a3466e7af5b491da0ab48f0d50711e193">CYHAL_UART_OUTPUT_TRIGGER_TX_FIFO_LEVEL_REACHED</a>
<br />
 }</td></tr>
<tr class="memdesc:ga79c475fe87b88afece099da885605075"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enum of possible output signals from a UART.  <a href="group__group__hal__uart.html#ga79c475fe87b88afece099da885605075">More...</a><br /></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga99424544773e74b40ee678570aaedf51"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga99424544773e74b40ee678570aaedf51">cyhal_uart_init</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, <a class="el" href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#ga707195ce0627016bf371643bdd9caa51">cyhal_gpio_t</a> tx, <a class="el" href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#ga707195ce0627016bf371643bdd9caa51">cyhal_gpio_t</a> rx, <a class="el" href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#ga707195ce0627016bf371643bdd9caa51">cyhal_gpio_t</a> cts, <a class="el" href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#ga707195ce0627016bf371643bdd9caa51">cyhal_gpio_t</a> rts, const <a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__clock__t">cyhal_clock_t</a> *clk, const <a class="el" href="group__group__hal__uart.html#structcyhal__uart__cfg__t">cyhal_uart_cfg_t</a> *cfg)</td></tr>
<tr class="memdesc:ga99424544773e74b40ee678570aaedf51"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the UART peripheral.  <a href="group__group__hal__uart.html#ga99424544773e74b40ee678570aaedf51">More...</a><br /></td></tr>
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<tr class="memitem:ga51731996aca653fc76caee4cc7ad684f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga51731996aca653fc76caee4cc7ad684f">cyhal_uart_free</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj)</td></tr>
<tr class="memdesc:ga51731996aca653fc76caee4cc7ad684f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Release the UART peripheral.  <a href="group__group__hal__uart.html#ga51731996aca653fc76caee4cc7ad684f">More...</a><br /></td></tr>
<tr class="separator:ga51731996aca653fc76caee4cc7ad684f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga14dcad3682e9b49e70b7f1e77cd862cc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga14dcad3682e9b49e70b7f1e77cd862cc">cyhal_uart_set_baud</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, uint32_t baudrate, uint32_t *actualbaud)</td></tr>
<tr class="memdesc:ga14dcad3682e9b49e70b7f1e77cd862cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the baud rate.  <a href="group__group__hal__uart.html#ga14dcad3682e9b49e70b7f1e77cd862cc">More...</a><br /></td></tr>
<tr class="separator:ga14dcad3682e9b49e70b7f1e77cd862cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4af8ba6ff0012214be498a001f1ac782"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga4af8ba6ff0012214be498a001f1ac782">cyhal_uart_configure</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, const <a class="el" href="group__group__hal__uart.html#structcyhal__uart__cfg__t">cyhal_uart_cfg_t</a> *cfg)</td></tr>
<tr class="memdesc:ga4af8ba6ff0012214be498a001f1ac782"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the data bits, stop bits, and parity.  <a href="group__group__hal__uart.html#ga4af8ba6ff0012214be498a001f1ac782">More...</a><br /></td></tr>
<tr class="separator:ga4af8ba6ff0012214be498a001f1ac782"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga89108b2d339dc9863ec660588e3a4a12"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga89108b2d339dc9863ec660588e3a4a12">cyhal_uart_getc</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, uint8_t *value, uint32_t timeout)</td></tr>
<tr class="memdesc:ga89108b2d339dc9863ec660588e3a4a12"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get a character.  <a href="group__group__hal__uart.html#ga89108b2d339dc9863ec660588e3a4a12">More...</a><br /></td></tr>
<tr class="separator:ga89108b2d339dc9863ec660588e3a4a12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2184202b0b3995fcf625caf9f8c3dc05"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga2184202b0b3995fcf625caf9f8c3dc05">cyhal_uart_putc</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, uint32_t value)</td></tr>
<tr class="memdesc:ga2184202b0b3995fcf625caf9f8c3dc05"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send a character.  <a href="group__group__hal__uart.html#ga2184202b0b3995fcf625caf9f8c3dc05">More...</a><br /></td></tr>
<tr class="separator:ga2184202b0b3995fcf625caf9f8c3dc05"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad85e26dd47eecd9705ab1931253c20f1"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#gad85e26dd47eecd9705ab1931253c20f1">cyhal_uart_readable</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj)</td></tr>
<tr class="memdesc:gad85e26dd47eecd9705ab1931253c20f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check the number of bytes available to read from the receive buffers.  <a href="group__group__hal__uart.html#gad85e26dd47eecd9705ab1931253c20f1">More...</a><br /></td></tr>
<tr class="separator:gad85e26dd47eecd9705ab1931253c20f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga760296fe084b3e0ab3cdd1fba745a8b3"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga760296fe084b3e0ab3cdd1fba745a8b3">cyhal_uart_writable</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj)</td></tr>
<tr class="memdesc:ga760296fe084b3e0ab3cdd1fba745a8b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check the number of bytes than can be written to the transmit buffer.  <a href="group__group__hal__uart.html#ga760296fe084b3e0ab3cdd1fba745a8b3">More...</a><br /></td></tr>
<tr class="separator:ga760296fe084b3e0ab3cdd1fba745a8b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc1932516baa1bd7285527a5a7456d75"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#gadc1932516baa1bd7285527a5a7456d75">cyhal_uart_clear</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj)</td></tr>
<tr class="memdesc:gadc1932516baa1bd7285527a5a7456d75"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the UART buffers.  <a href="group__group__hal__uart.html#gadc1932516baa1bd7285527a5a7456d75">More...</a><br /></td></tr>
<tr class="separator:gadc1932516baa1bd7285527a5a7456d75"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacd188597425e7bbf4536082277248e9f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#gacd188597425e7bbf4536082277248e9f">cyhal_uart_enable_flow_control</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, bool enable_cts, bool enable_rts)</td></tr>
<tr class="memdesc:gacd188597425e7bbf4536082277248e9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure the UART for flow control.  <a href="group__group__hal__uart.html#gacd188597425e7bbf4536082277248e9f">More...</a><br /></td></tr>
<tr class="separator:gacd188597425e7bbf4536082277248e9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2be8141bcc5fcc349b0dce1c09c4e98f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga2be8141bcc5fcc349b0dce1c09c4e98f">cyhal_uart_write</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, void *tx, size_t *tx_length)</td></tr>
<tr class="memdesc:ga2be8141bcc5fcc349b0dce1c09c4e98f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Begin synchronous TX transfer.  <a href="group__group__hal__uart.html#ga2be8141bcc5fcc349b0dce1c09c4e98f">More...</a><br /></td></tr>
<tr class="separator:ga2be8141bcc5fcc349b0dce1c09c4e98f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae436ac5108e3bc92f439c66c315e07ca"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#gae436ac5108e3bc92f439c66c315e07ca">cyhal_uart_read</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, void *rx, size_t *rx_length)</td></tr>
<tr class="memdesc:gae436ac5108e3bc92f439c66c315e07ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Begin synchronous RX transfer (enable interrupt for data collecting)  <a href="group__group__hal__uart.html#gae436ac5108e3bc92f439c66c315e07ca">More...</a><br /></td></tr>
<tr class="separator:gae436ac5108e3bc92f439c66c315e07ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb84cac4753a07555c98cfd7c95d4dce"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#gadb84cac4753a07555c98cfd7c95d4dce">cyhal_uart_set_async_mode</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, <a class="el" href="group__group__hal__general__types.html#gab2d2acfb82599df54152be0b170c6ec2">cyhal_async_mode_t</a> mode, uint8_t dma_priority)</td></tr>
<tr class="memdesc:gadb84cac4753a07555c98cfd7c95d4dce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the mechanism that is used to perform UART asynchronous transfers.  <a href="group__group__hal__uart.html#gadb84cac4753a07555c98cfd7c95d4dce">More...</a><br /></td></tr>
<tr class="separator:gadb84cac4753a07555c98cfd7c95d4dce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab569e52660c519b775e3a15f3e2dbb46"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#gab569e52660c519b775e3a15f3e2dbb46">cyhal_uart_write_async</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, void *tx, size_t length)</td></tr>
<tr class="memdesc:gab569e52660c519b775e3a15f3e2dbb46"><td class="mdescLeft">&#160;</td><td class="mdescRight">Begin asynchronous TX transfer.  <a href="group__group__hal__uart.html#gab569e52660c519b775e3a15f3e2dbb46">More...</a><br /></td></tr>
<tr class="separator:gab569e52660c519b775e3a15f3e2dbb46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga00ef108f7ee7beba3d5090b2e506b54f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga00ef108f7ee7beba3d5090b2e506b54f">cyhal_uart_read_async</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, void *rx, size_t length)</td></tr>
<tr class="memdesc:ga00ef108f7ee7beba3d5090b2e506b54f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Begin asynchronous RX transfer.  <a href="group__group__hal__uart.html#ga00ef108f7ee7beba3d5090b2e506b54f">More...</a><br /></td></tr>
<tr class="separator:ga00ef108f7ee7beba3d5090b2e506b54f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ee15173efae0edfa0813e8b78a1a467"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga5ee15173efae0edfa0813e8b78a1a467">cyhal_uart_is_tx_active</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj)</td></tr>
<tr class="memdesc:ga5ee15173efae0edfa0813e8b78a1a467"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determines if the UART peripheral is currently in use for TX.  <a href="group__group__hal__uart.html#ga5ee15173efae0edfa0813e8b78a1a467">More...</a><br /></td></tr>
<tr class="separator:ga5ee15173efae0edfa0813e8b78a1a467"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84bd3dc69297980c77697dcecbac4a57"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga84bd3dc69297980c77697dcecbac4a57">cyhal_uart_is_rx_active</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj)</td></tr>
<tr class="memdesc:ga84bd3dc69297980c77697dcecbac4a57"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determines if the UART peripheral is currently in use for RX.  <a href="group__group__hal__uart.html#ga84bd3dc69297980c77697dcecbac4a57">More...</a><br /></td></tr>
<tr class="separator:ga84bd3dc69297980c77697dcecbac4a57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa143498ce81a014c19bcd1e8ad43a3f6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#gaa143498ce81a014c19bcd1e8ad43a3f6">cyhal_uart_write_abort</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj)</td></tr>
<tr class="memdesc:gaa143498ce81a014c19bcd1e8ad43a3f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Abort the ongoing TX transaction.  <a href="group__group__hal__uart.html#gaa143498ce81a014c19bcd1e8ad43a3f6">More...</a><br /></td></tr>
<tr class="separator:gaa143498ce81a014c19bcd1e8ad43a3f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga94980c5a10527027be1da8e11bc34a98"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga94980c5a10527027be1da8e11bc34a98">cyhal_uart_read_abort</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj)</td></tr>
<tr class="memdesc:ga94980c5a10527027be1da8e11bc34a98"><td class="mdescLeft">&#160;</td><td class="mdescRight">Abort the ongoing read transaction.  <a href="group__group__hal__uart.html#ga94980c5a10527027be1da8e11bc34a98">More...</a><br /></td></tr>
<tr class="separator:ga94980c5a10527027be1da8e11bc34a98"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae26bab64811713b1d69170352fe32c20"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#gae26bab64811713b1d69170352fe32c20">cyhal_uart_register_callback</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, <a class="el" href="group__group__hal__uart.html#gac444f4c849b289d99a75e0132f04fb65">cyhal_uart_event_callback_t</a> callback, void *callback_arg)</td></tr>
<tr class="memdesc:gae26bab64811713b1d69170352fe32c20"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register a uart callback handler.  <a href="group__group__hal__uart.html#gae26bab64811713b1d69170352fe32c20">More...</a><br /></td></tr>
<tr class="separator:gae26bab64811713b1d69170352fe32c20"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4dae4cef7dbf1d7935fe6dd6d31f282e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga4dae4cef7dbf1d7935fe6dd6d31f282e">cyhal_uart_enable_event</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, <a class="el" href="group__group__hal__uart.html#gaf307283f3d358e4b6048846034df19aa">cyhal_uart_event_t</a> event, uint8_t intr_priority, bool enable)</td></tr>
<tr class="memdesc:ga4dae4cef7dbf1d7935fe6dd6d31f282e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable or disable specified UART events.  <a href="group__group__hal__uart.html#ga4dae4cef7dbf1d7935fe6dd6d31f282e">More...</a><br /></td></tr>
<tr class="separator:ga4dae4cef7dbf1d7935fe6dd6d31f282e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaea15b10b90d93252206f19b1bbdd0f47"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#gaea15b10b90d93252206f19b1bbdd0f47">cyhal_uart_set_fifo_level</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, <a class="el" href="group__group__hal__uart.html#ga17602199b64430d4b5503e14340c4ca0">cyhal_uart_fifo_type_t</a> type, uint16_t level)</td></tr>
<tr class="memdesc:gaea15b10b90d93252206f19b1bbdd0f47"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets a threshold level for a FIFO that will generate an interrupt and a trigger output.  <a href="group__group__hal__uart.html#gaea15b10b90d93252206f19b1bbdd0f47">More...</a><br /></td></tr>
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<tr class="memitem:gac26f415eecf9b66b490bac95bddab362"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#gac26f415eecf9b66b490bac95bddab362">cyhal_uart_enable_output</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, <a class="el" href="group__group__hal__uart.html#ga79c475fe87b88afece099da885605075">cyhal_uart_output_t</a> output, <a class="el" href="group__group__hal__impl__triggers__psoc6__01.html#ga96236d1368f920d28af90262e8b57046">cyhal_source_t</a> *source)</td></tr>
<tr class="memdesc:gac26f415eecf9b66b490bac95bddab362"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the specified output signal from a UART.  <a href="group__group__hal__uart.html#gac26f415eecf9b66b490bac95bddab362">More...</a><br /></td></tr>
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<tr class="memitem:ga858d1257386c23c97da3b3aff539a162"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga858d1257386c23c97da3b3aff539a162">cyhal_uart_disable_output</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, <a class="el" href="group__group__hal__uart.html#ga79c475fe87b88afece099da885605075">cyhal_uart_output_t</a> output)</td></tr>
<tr class="memdesc:ga858d1257386c23c97da3b3aff539a162"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables the specified output signal from a UART.  <a href="group__group__hal__uart.html#ga858d1257386c23c97da3b3aff539a162">More...</a><br /></td></tr>
<tr class="separator:ga858d1257386c23c97da3b3aff539a162"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabf5886f9c8e5a1afc47f6a3be99ab256"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#gabf5886f9c8e5a1afc47f6a3be99ab256">cyhal_uart_init_cfg</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, const <a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__configurator__t">cyhal_uart_configurator_t</a> *cfg)</td></tr>
<tr class="memdesc:gabf5886f9c8e5a1afc47f6a3be99ab256"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the UART peripheral using a configurator generated configuration struct.  <a href="group__group__hal__uart.html#gabf5886f9c8e5a1afc47f6a3be99ab256">More...</a><br /></td></tr>
<tr class="separator:gabf5886f9c8e5a1afc47f6a3be99ab256"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga76eddcf3f061a3984819bc8dfe503ae5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__uart.html#ga76eddcf3f061a3984819bc8dfe503ae5">cyhal_uart_config_software_buffer</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *obj, uint8_t *rx_buffer, uint32_t rx_buffer_size)</td></tr>
<tr class="memdesc:ga76eddcf3f061a3984819bc8dfe503ae5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure UART RX software buffer, which will extend the hardware RX FIFO buffer only for SW async mode.  <a href="group__group__hal__uart.html#ga76eddcf3f061a3984819bc8dfe503ae5">More...</a><br /></td></tr>
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</table>
<hr/><h2 class="groupheader">Data Structure Documentation</h2>
<a name="structcyhal__uart__cfg__t" id="structcyhal__uart__cfg__t"></a>
<h2 class="memtitle"><span class="permalink"><a href="#structcyhal__uart__cfg__t">&#9670;&nbsp;</a></span>cyhal_uart_cfg_t</h2>

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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">struct cyhal_uart_cfg_t</td>
        </tr>
      </table>
</div><div class="memdoc">
<table class="fieldtable">
<tr><th colspan="3">Data Fields</th></tr>
<tr><td class="fieldtype">
<a id="a3360061aafad236eb9a9d347f9154643" name="a3360061aafad236eb9a9d347f9154643"></a>uint32_t</td>
<td class="fieldname">
data_bits</td>
<td class="fielddoc">
The number of data bits (generally 8 or 9) </td></tr>
<tr><td class="fieldtype">
<a id="a6864a54db95005a564fd8617f9029e20" name="a6864a54db95005a564fd8617f9029e20"></a>uint32_t</td>
<td class="fieldname">
stop_bits</td>
<td class="fielddoc">
The number of stop bits (generally 0 or 1) </td></tr>
<tr><td class="fieldtype">
<a id="a70b51afc79e56af7360a9b35de3fdb0e" name="a70b51afc79e56af7360a9b35de3fdb0e"></a><a class="el" href="group__group__hal__uart.html#ga410f06ac3fe5576220caf146fda6b77b">cyhal_uart_parity_t</a></td>
<td class="fieldname">
parity</td>
<td class="fielddoc">
The parity. </td></tr>
<tr><td class="fieldtype">
<a id="abf31b7706f129f2ea59471ba7fb6835a" name="abf31b7706f129f2ea59471ba7fb6835a"></a>uint8_t *</td>
<td class="fieldname">
rx_buffer</td>
<td class="fielddoc">
The rx software buffer pointer, if NULL, no rx software buffer will be used. </td></tr>
<tr><td class="fieldtype">
<a id="a3ab4d4e2c33ec8ba1a0943e1f24d61f1" name="a3ab4d4e2c33ec8ba1a0943e1f24d61f1"></a>uint32_t</td>
<td class="fieldname">
rx_buffer_size</td>
<td class="fielddoc">
The number of bytes in the rx software buffer. </td></tr>
</table>

</div>
</div>
<h2 class="groupheader">Enumeration Type Documentation</h2>
<a id="ga410f06ac3fe5576220caf146fda6b77b" name="ga410f06ac3fe5576220caf146fda6b77b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga410f06ac3fe5576220caf146fda6b77b">&#9670;&nbsp;</a></span>cyhal_uart_parity_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__hal__uart.html#ga410f06ac3fe5576220caf146fda6b77b">cyhal_uart_parity_t</a></td>
        </tr>
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</div><div class="memdoc">

<p>UART Parity. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga410f06ac3fe5576220caf146fda6b77ba327098a8b49fceb10e330d561019d8cb" name="gga410f06ac3fe5576220caf146fda6b77ba327098a8b49fceb10e330d561019d8cb"></a>CYHAL_UART_PARITY_NONE&#160;</td><td class="fielddoc"><p >UART has no parity check <br  />
 </p>
</td></tr>
<tr><td class="fieldname"><a id="gga410f06ac3fe5576220caf146fda6b77ba47c0ca4d5811d418e1bdaea54da62f7f" name="gga410f06ac3fe5576220caf146fda6b77ba47c0ca4d5811d418e1bdaea54da62f7f"></a>CYHAL_UART_PARITY_EVEN&#160;</td><td class="fielddoc"><p >UART has even parity check. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga410f06ac3fe5576220caf146fda6b77bad3844eeec5198449f882f5b3509282ea" name="gga410f06ac3fe5576220caf146fda6b77bad3844eeec5198449f882f5b3509282ea"></a>CYHAL_UART_PARITY_ODD&#160;</td><td class="fielddoc"><p >UART has odd parity check <br  />
 </p>
</td></tr>
</table>

</div>
</div>
<a id="gaf307283f3d358e4b6048846034df19aa" name="gaf307283f3d358e4b6048846034df19aa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaf307283f3d358e4b6048846034df19aa">&#9670;&nbsp;</a></span>cyhal_uart_event_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__hal__uart.html#gaf307283f3d358e4b6048846034df19aa">cyhal_uart_event_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enum to enable/disable/report interrupt cause flags. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ggaf307283f3d358e4b6048846034df19aaadc15f333858441e62e2de2408a5ac767" name="ggaf307283f3d358e4b6048846034df19aaadc15f333858441e62e2de2408a5ac767"></a>CYHAL_UART_IRQ_NONE&#160;</td><td class="fielddoc"><p >No interrupt. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf307283f3d358e4b6048846034df19aaaafb0642f2b2672db3ab4446e4c075864" name="ggaf307283f3d358e4b6048846034df19aaaafb0642f2b2672db3ab4446e4c075864"></a>CYHAL_UART_IRQ_TX_TRANSMIT_IN_FIFO&#160;</td><td class="fielddoc"><p >All TX data from transmit has been moved to the HW TX FIFO buffer. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf307283f3d358e4b6048846034df19aaa656718b2b8343a46a64478b1d415bfc4" name="ggaf307283f3d358e4b6048846034df19aaa656718b2b8343a46a64478b1d415bfc4"></a>CYHAL_UART_IRQ_TX_DONE&#160;</td><td class="fielddoc"><p >All TX data has been transmitted (applicable only for cyhal_uart_write_async) </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf307283f3d358e4b6048846034df19aaa9984c9f5e7f3b57c9740d390c35388db" name="ggaf307283f3d358e4b6048846034df19aaa9984c9f5e7f3b57c9740d390c35388db"></a>CYHAL_UART_IRQ_TX_ERROR&#160;</td><td class="fielddoc"><p >An error occurred during TX. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf307283f3d358e4b6048846034df19aaa7d073741825cc32b1be09fa59d6c8123" name="ggaf307283f3d358e4b6048846034df19aaa7d073741825cc32b1be09fa59d6c8123"></a>CYHAL_UART_IRQ_RX_FULL&#160;</td><td class="fielddoc"><p >The SW RX buffer (if used) is full. Additional data will be stored in the HW RX FIFO buffer. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf307283f3d358e4b6048846034df19aaac2db86894106691360ad64c35d33b578" name="ggaf307283f3d358e4b6048846034df19aaac2db86894106691360ad64c35d33b578"></a>CYHAL_UART_IRQ_RX_DONE&#160;</td><td class="fielddoc"><p >All RX data has been received (applicable only for cyhal_uart_read_async) </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf307283f3d358e4b6048846034df19aaa7f5d1f47a602c8ac0df06c121bf4ce46" name="ggaf307283f3d358e4b6048846034df19aaa7f5d1f47a602c8ac0df06c121bf4ce46"></a>CYHAL_UART_IRQ_RX_ERROR&#160;</td><td class="fielddoc"><p >An error occurred during RX. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf307283f3d358e4b6048846034df19aaa9b64ead890054ee5943b58bafc0f367e" name="ggaf307283f3d358e4b6048846034df19aaa9b64ead890054ee5943b58bafc0f367e"></a>CYHAL_UART_IRQ_RX_NOT_EMPTY&#160;</td><td class="fielddoc"><p >The HW RX FIFO buffer is not empty. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf307283f3d358e4b6048846034df19aaa0c7868cf2a2719db7fc2cb8c357e47a9" name="ggaf307283f3d358e4b6048846034df19aaa0c7868cf2a2719db7fc2cb8c357e47a9"></a>CYHAL_UART_IRQ_TX_EMPTY&#160;</td><td class="fielddoc"><p >The HW TX FIFO buffer is empty. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf307283f3d358e4b6048846034df19aaac116ebc0ab3ebc77dffd457f904ae029" name="ggaf307283f3d358e4b6048846034df19aaac116ebc0ab3ebc77dffd457f904ae029"></a>CYHAL_UART_IRQ_TX_FIFO&#160;</td><td class="fielddoc"><p >Number of entries in the HW TX FIFO is less than the TX FIFO trigger level. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggaf307283f3d358e4b6048846034df19aaa1f0edecb2e607d340d868cdd997a16d3" name="ggaf307283f3d358e4b6048846034df19aaa1f0edecb2e607d340d868cdd997a16d3"></a>CYHAL_UART_IRQ_RX_FIFO&#160;</td><td class="fielddoc"><p >Number of entries in the HW RX FIFO is more than the RX FIFO trigger level. </p>
</td></tr>
</table>

</div>
</div>
<a id="ga17602199b64430d4b5503e14340c4ca0" name="ga17602199b64430d4b5503e14340c4ca0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga17602199b64430d4b5503e14340c4ca0">&#9670;&nbsp;</a></span>cyhal_uart_fifo_type_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__hal__uart.html#ga17602199b64430d4b5503e14340c4ca0">cyhal_uart_fifo_type_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>UART FIFO type. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga17602199b64430d4b5503e14340c4ca0ae0cb3a0275909eb435e1d892dcc6703c" name="gga17602199b64430d4b5503e14340c4ca0ae0cb3a0275909eb435e1d892dcc6703c"></a>CYHAL_UART_FIFO_RX&#160;</td><td class="fielddoc"><p >Set RX FIFO level. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga17602199b64430d4b5503e14340c4ca0a2e87281f1bf6b951e55f23edc21e606e" name="gga17602199b64430d4b5503e14340c4ca0a2e87281f1bf6b951e55f23edc21e606e"></a>CYHAL_UART_FIFO_TX&#160;</td><td class="fielddoc"><p >Set TX FIFO level. </p>
</td></tr>
</table>

</div>
</div>
<a id="ga79c475fe87b88afece099da885605075" name="ga79c475fe87b88afece099da885605075"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga79c475fe87b88afece099da885605075">&#9670;&nbsp;</a></span>cyhal_uart_output_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__hal__uart.html#ga79c475fe87b88afece099da885605075">cyhal_uart_output_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enum of possible output signals from a UART. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga79c475fe87b88afece099da885605075a726f4bf351f0fd57da573087def9745c" name="gga79c475fe87b88afece099da885605075a726f4bf351f0fd57da573087def9745c"></a>CYHAL_UART_OUTPUT_TRIGGER_RX_FIFO_LEVEL_REACHED&#160;</td><td class="fielddoc"><p >Output the RX FIFO signal which is triggered when the receive FIFO has more entries than the configured level. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga79c475fe87b88afece099da885605075a3466e7af5b491da0ab48f0d50711e193" name="gga79c475fe87b88afece099da885605075a3466e7af5b491da0ab48f0d50711e193"></a>CYHAL_UART_OUTPUT_TRIGGER_TX_FIFO_LEVEL_REACHED&#160;</td><td class="fielddoc"><p >Output the TX FIFO signal which is triggered when the transmit FIFO has less entries than the configured level. </p>
</td></tr>
</table>

</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
<a id="ga99424544773e74b40ee678570aaedf51" name="ga99424544773e74b40ee678570aaedf51"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga99424544773e74b40ee678570aaedf51">&#9670;&nbsp;</a></span>cyhal_uart_init()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_uart_init </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *&#160;</td>
          <td class="paramname"><em>obj</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#ga707195ce0627016bf371643bdd9caa51">cyhal_gpio_t</a>&#160;</td>
          <td class="paramname"><em>tx</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#ga707195ce0627016bf371643bdd9caa51">cyhal_gpio_t</a>&#160;</td>
          <td class="paramname"><em>rx</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#ga707195ce0627016bf371643bdd9caa51">cyhal_gpio_t</a>&#160;</td>
          <td class="paramname"><em>cts</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__pin__package__psoc6__01__104__m__csp__ble.html#ga707195ce0627016bf371643bdd9caa51">cyhal_gpio_t</a>&#160;</td>
          <td class="paramname"><em>rts</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">const <a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__clock__t">cyhal_clock_t</a> *&#160;</td>
          <td class="paramname"><em>clk</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">const <a class="el" href="group__group__hal__uart.html#structcyhal__uart__cfg__t">cyhal_uart_cfg_t</a> *&#160;</td>
          <td class="paramname"><em>cfg</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Initialize the UART peripheral. </p>
<dl class="section note"><dt>Note</dt><dd>This will set the baud rate to a default of <a class="el" href="group__group__hal__uart.html#ga4b2c1534032adfc825026b5882fa2cd6">CYHAL_UART_DEFAULT_BAUD</a>. This can be changed by calling <a class="el" href="group__group__hal__uart.html#ga14dcad3682e9b49e70b7f1e77cd862cc">cyhal_uart_set_baud</a>. </dd>
<dd>
Function activates the flow control feature if CTS / RTS pins are provided.</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[out]</td><td class="paramname">obj</td><td>Pointer to a UART object. The caller must allocate the memory for this object but the init function will initialize its contents. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">tx</td><td>The TX pin name, if no TX pin use NC </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">rx</td><td>The RX pin name, if no RX pin use NC </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">cts</td><td>The CTS pin name, if no CTS pin use NC </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">rts</td><td>The RTS pin name, if no RTS pin use NC </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">clk</td><td>The clock to use can be shared. If not provided, a new clock will be allocated and the default baud rate will be set </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">cfg</td><td>The UART configuration data for data bits, stop bits and parity. If not provided, default values of (8, 1, none) will be used </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the init request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga51731996aca653fc76caee4cc7ad684f">&#9670;&nbsp;</a></span>cyhal_uart_free()</h2>

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<p>Release the UART peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">obj</td><td>The UART object </td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga14dcad3682e9b49e70b7f1e77cd862cc">&#9670;&nbsp;</a></span>cyhal_uart_set_baud()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_uart_set_baud </td>
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        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>baudrate</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t *&#160;</td>
          <td class="paramname"><em>actualbaud</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Configure the baud rate. </p>
<dl class="section note"><dt>Note</dt><dd>This function should only be called if a shared clock divider is not used i.e. the clock parameter is set to NULL when calling <a class="el" href="group__group__hal__uart.html#ga99424544773e74b40ee678570aaedf51">cyhal_uart_init</a>.</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">baudrate</td><td>The baud rate to be configured </td></tr>
    <tr><td class="paramdir">[out]</td><td class="paramname">actualbaud</td><td>The actual baud rate achieved by the HAL Specify NULL if you do not want this information. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the set_baud request </dd></dl>

</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga4af8ba6ff0012214be498a001f1ac782">&#9670;&nbsp;</a></span>cyhal_uart_configure()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_uart_configure </td>
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        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">const <a class="el" href="group__group__hal__uart.html#structcyhal__uart__cfg__t">cyhal_uart_cfg_t</a> *&#160;</td>
          <td class="paramname"><em>cfg</em>&#160;</td>
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          <td>)</td>
          <td></td><td></td>
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<p>Configure the data bits, stop bits, and parity. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">cfg</td><td>The UART configuration data for data bits, stop bits and parity. rx_buffer and rx_buffer_size are ignored. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the configure request </dd></dl>

</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga89108b2d339dc9863ec660588e3a4a12">&#9670;&nbsp;</a></span>cyhal_uart_getc()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_uart_getc </td>
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          <td class="paramtype"><a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *&#160;</td>
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        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint8_t *&#160;</td>
          <td class="paramname"><em>value</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>timeout</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>Get a character. </p>
<p >This is a blocking call which waits till a character is received.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[out]</td><td class="paramname">value</td><td>The value read from the serial port </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">timeout</td><td>The time in ms to spend attempting to receive from serial port. Zero is wait forever </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the getc request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2184202b0b3995fcf625caf9f8c3dc05">&#9670;&nbsp;</a></span>cyhal_uart_putc()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_uart_putc </td>
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          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>&#160;</td>
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          <td>)</td>
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<p>Send a character. </p>
<p >This is a blocking call which waits till the character is sent out from the UART completely.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>The character to be sent </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the putc request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gad85e26dd47eecd9705ab1931253c20f1">&#9670;&nbsp;</a></span>cyhal_uart_readable()</h2>

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<p>Check the number of bytes available to read from the receive buffers. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The number of readable bytes </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga760296fe084b3e0ab3cdd1fba745a8b3">&#9670;&nbsp;</a></span>cyhal_uart_writable()</h2>

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<p>Check the number of bytes than can be written to the transmit buffer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The number of bytes that can be written </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gadc1932516baa1bd7285527a5a7456d75">&#9670;&nbsp;</a></span>cyhal_uart_clear()</h2>

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<p>Clear the UART buffers. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the clear request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gacd188597425e7bbf4536082277248e9f">&#9670;&nbsp;</a></span>cyhal_uart_enable_flow_control()</h2>

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          <td class="paramtype"><a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *&#160;</td>
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        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>enable_cts</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>enable_rts</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
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<p>Configure the UART for flow control. </p>
<p >It sets flow control in the hardware if a UART peripheral supports it, otherwise software emulation is used.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">enable_cts</td><td>Enable or disable CTS functionality </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">enable_rts</td><td>Enable or disable RTS functionality </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the enable_flow_control request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2be8141bcc5fcc349b0dce1c09c4e98f">&#9670;&nbsp;</a></span>cyhal_uart_write()</h2>

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          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>tx</em>, </td>
        </tr>
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          <td></td>
          <td class="paramtype">size_t *&#160;</td>
          <td class="paramname"><em>tx_length</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p>Begin synchronous TX transfer. </p>
<p >This will write either <code>length</code> bytes or until the write buffer is full, whichever is less, then return. The value pointed to by <code>length</code> will be updated to reflect the number of bytes that was actually written.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">tx</td><td>The transmit buffer </td></tr>
    <tr><td class="paramdir">[in,out]</td><td class="paramname">tx_length</td><td>[in] The number of bytes to transmit, [out] number actually transmitted </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the tx request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gae436ac5108e3bc92f439c66c315e07ca">&#9670;&nbsp;</a></span>cyhal_uart_read()</h2>

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          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>rx</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">size_t *&#160;</td>
          <td class="paramname"><em>rx_length</em>&#160;</td>
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          <td>)</td>
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<p>Begin synchronous RX transfer (enable interrupt for data collecting) </p>
<p >This will read either <code>length</code> bytes or the number of bytes that are currently available in the receive buffer, whichever is less, then return. The value pointed to by <code>length</code> will be updated to reflect the number of bytes that was actually read.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">rx</td><td>The receive buffer </td></tr>
    <tr><td class="paramdir">[in,out]</td><td class="paramname">rx_length</td><td>[in] The number of bytes to receive, [out] number actually received </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the rx request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gadb84cac4753a07555c98cfd7c95d4dce">&#9670;&nbsp;</a></span>cyhal_uart_set_async_mode()</h2>

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          <td class="paramtype"><a class="el" href="group__group__hal__general__types.html#gab2d2acfb82599df54152be0b170c6ec2">cyhal_async_mode_t</a>&#160;</td>
          <td class="paramname"><em>mode</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>dma_priority</em>&#160;</td>
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<p>Set the mechanism that is used to perform UART asynchronous transfers. </p>
<p >The default is SW. </p><dl class="section warning"><dt>Warning</dt><dd>The effect of calling this function while an async transfer is pending is undefined.</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>The transfer mode </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">dma_priority</td><td>The priority, if DMA is used. Valid values are the same as for <a class="el" href="group__group__hal__dma.html#gab9c200507a8ee87b894150416e4f5dd1">cyhal_dma_init</a>. If DMA is not selected, the only valid value is CYHAL_DMA_PRIORITY_DEFAULT, and no guarantees are made about prioritization. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the set mode request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gab569e52660c519b775e3a15f3e2dbb46">&#9670;&nbsp;</a></span>cyhal_uart_write_async()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_uart_write_async </td>
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          <td class="paramkey"></td>
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          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>tx</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
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          <td class="paramtype">size_t&#160;</td>
          <td class="paramname"><em>length</em>&#160;</td>
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<p>Begin asynchronous TX transfer. </p>
<p >This will transfer <code>length</code> bytes into the buffer pointed to by <code>tx</code> in the background. When the requested quantity of data has been transferred, the <a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaaafb0642f2b2672db3ab4446e4c075864">CYHAL_UART_IRQ_TX_TRANSMIT_IN_FIFO</a> event will be raised. The transmit buffer is a user defined buffer that will be sent on the UART. The user must register a callback with <a class="el" href="group__group__hal__uart.html#gae26bab64811713b1d69170352fe32c20">cyhal_uart_register_callback</a>. If desired, TX callback events can be enabled using <a class="el" href="group__group__hal__uart.html#ga4dae4cef7dbf1d7935fe6dd6d31f282e">cyhal_uart_enable_event</a> with the appropriate events.</p>
<p >If D-cache is enabled and data Cache line is 32 bytes, the user needs to make sure that the tx pointer passed to the cyhal_uart_write_async function points to a 32 byte aligned array of words that contains the buffer data. The size of buffer data must be a multiple of 32 bytes to ensure cache coherency. CY_ALIGN(__SCB_DCACHE_LINE_SIZE) macro can be used for 32 byte alignment.</p>
<p >Refer to <a class="el" href="md_source_hal_dcache.html#DCACHE_Management">DCACHE_Management</a> for more information.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">tx</td><td>The transmit buffer </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">length</td><td>The number of bytes to transmit </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the tx_async request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga00ef108f7ee7beba3d5090b2e506b54f">&#9670;&nbsp;</a></span>cyhal_uart_read_async()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_uart_read_async </td>
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          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>rx</em>, </td>
        </tr>
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          <td></td>
          <td class="paramtype">size_t&#160;</td>
          <td class="paramname"><em>length</em>&#160;</td>
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          <td>)</td>
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<p>Begin asynchronous RX transfer. </p>
<p >This will transfer <code>length</code> bytes into the buffer pointed to by <code>rx</code> in the background. When the requested quantity of data has been transferred, the <a class="el" href="group__group__hal__uart.html#ggaf307283f3d358e4b6048846034df19aaac2db86894106691360ad64c35d33b578">CYHAL_UART_IRQ_RX_DONE</a> event will be raised. Received data is placed in the user specified buffer. The user must register a callback with <a class="el" href="group__group__hal__uart.html#gae26bab64811713b1d69170352fe32c20">cyhal_uart_register_callback</a>. RX callback events can be enabled using <a class="el" href="group__group__hal__uart.html#ga4dae4cef7dbf1d7935fe6dd6d31f282e">cyhal_uart_enable_event</a> with the appropriate events.</p>
<p >If D-cache is enabled and data Cache line is 32 bytes, the user needs to make sure that the tx pointer passed to the cyhal_uart_read_async function points to a 32 byte aligned array of words that contains the buffer data. The size of buffer data must be a multiple of 32 bytes to ensure cache coherency. CY_ALIGN(__SCB_DCACHE_LINE_SIZE) macro can be used for 32 byte alignment.</p>
<p >Refer to <a class="el" href="md_source_hal_dcache.html#DCACHE_Management">DCACHE_Management</a> for more information.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[out]</td><td class="paramname">rx</td><td>The user specified receive buffer </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">length</td><td>The number of bytes to receive </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the rx_async request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5ee15173efae0edfa0813e8b78a1a467">&#9670;&nbsp;</a></span>cyhal_uart_is_tx_active()</h2>

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<p>Determines if the UART peripheral is currently in use for TX. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>TX channel active status (active=true) </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga84bd3dc69297980c77697dcecbac4a57">&#9670;&nbsp;</a></span>cyhal_uart_is_rx_active()</h2>

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<p>Determines if the UART peripheral is currently in use for RX. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>RX channel active status (active=true) </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gaa143498ce81a014c19bcd1e8ad43a3f6">&#9670;&nbsp;</a></span>cyhal_uart_write_abort()</h2>

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<p>Abort the ongoing TX transaction. </p>
<p >Disables the TX interrupt and flushes the TX hardware buffer if TX FIFO is used.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the tx_abort request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga94980c5a10527027be1da8e11bc34a98">&#9670;&nbsp;</a></span>cyhal_uart_read_abort()</h2>

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<p>Abort the ongoing read transaction. </p>
<p >Disables the RX interrupt and flushes the RX hardware buffer if RX FIFO is used.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the read_abort request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gae26bab64811713b1d69170352fe32c20">&#9670;&nbsp;</a></span>cyhal_uart_register_callback()</h2>

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          <td class="paramname"><em>callback</em>, </td>
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          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>callback_arg</em>&#160;</td>
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<p>Register a uart callback handler. </p>
<p >This function will be called when one of the events enabled by <a class="el" href="group__group__hal__uart.html#ga4dae4cef7dbf1d7935fe6dd6d31f282e">cyhal_uart_enable_event</a> occurs.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">callback</td><td>The callback handler which will be invoked when the interrupt fires </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">callback_arg</td><td>Generic argument that will be provided to the callback when called </td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga4dae4cef7dbf1d7935fe6dd6d31f282e">&#9670;&nbsp;</a></span>cyhal_uart_enable_event()</h2>

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          <td class="paramtype"><a class="el" href="group__group__hal__uart.html#gaf307283f3d358e4b6048846034df19aa">cyhal_uart_event_t</a>&#160;</td>
          <td class="paramname"><em>event</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>intr_priority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>enable</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Enable or disable specified UART events. </p>
<p >When an enabled event occurs, the function specified by <a class="el" href="group__group__hal__uart.html#gae26bab64811713b1d69170352fe32c20">cyhal_uart_register_callback</a> will be called.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">event</td><td>The uart event type, this argument supports the bitwise-or of multiple enum flag values </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">intr_priority</td><td>The priority for NVIC interrupt events </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>True to turn on interrupts, False to turn off </td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gaea15b10b90d93252206f19b1bbdd0f47">&#9670;&nbsp;</a></span>cyhal_uart_set_fifo_level()</h2>

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          <td class="paramname"><em>type</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint16_t&#160;</td>
          <td class="paramname"><em>level</em>&#160;</td>
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          <td></td>
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<p>Sets a threshold level for a FIFO that will generate an interrupt and a trigger output. </p>
<p >The RX FIFO interrupt and trigger will be activated when the receive FIFO has more entries than the threshold. The TX FIFO interrupt and trigger will be activated when the transmit FIFO has less entries than the threshold.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">type</td><td>FIFO type to set level for </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">level</td><td>Level threshold to set </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the level set </dd></dl>

</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gac26f415eecf9b66b490bac95bddab362">&#9670;&nbsp;</a></span>cyhal_uart_enable_output()</h2>

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          <td class="paramname"><em>source</em>&#160;</td>
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<p>Enables the specified output signal from a UART. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">output</td><td>Which output signal to enable </td></tr>
    <tr><td class="paramdir">[out]</td><td class="paramname">source</td><td>Pointer to user-allocated source signal object which will be initialized by enable_output. <code>source</code> should be passed to (dis)connect_digital functions to (dis)connect the associated endpoints. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the output enable </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga858d1257386c23c97da3b3aff539a162">&#9670;&nbsp;</a></span>cyhal_uart_disable_output()</h2>

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<p>Disables the specified output signal from a UART. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">output</td><td>Which output signal to disable </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the output disable </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gabf5886f9c8e5a1afc47f6a3be99ab256">&#9670;&nbsp;</a></span>cyhal_uart_init_cfg()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_uart_init_cfg </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *&#160;</td>
          <td class="paramname"><em>obj</em>, </td>
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          <td class="paramtype">const <a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__configurator__t">cyhal_uart_configurator_t</a> *&#160;</td>
          <td class="paramname"><em>cfg</em>&#160;</td>
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<p>Initialize the UART peripheral using a configurator generated configuration struct. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART peripheral to configure </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">cfg</td><td>Configuration structure generated by a configurator. </td></tr>
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  </dd>
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<dl class="section return"><dt>Returns</dt><dd>The status of the operation </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga76eddcf3f061a3984819bc8dfe503ae5">&#9670;&nbsp;</a></span>cyhal_uart_config_software_buffer()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_uart_config_software_buffer </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__uart__t">cyhal_uart_t</a> *&#160;</td>
          <td class="paramname"><em>obj</em>, </td>
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          <td class="paramtype">uint8_t *&#160;</td>
          <td class="paramname"><em>rx_buffer</em>, </td>
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          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>rx_buffer_size</em>&#160;</td>
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<p>Configure UART RX software buffer, which will extend the hardware RX FIFO buffer only for SW async mode. </p>
<p ><a class="el" href="group__group__hal__uart.html#ga99424544773e74b40ee678570aaedf51">cyhal_uart_init</a> function does not require this function call if a non-null value was provided for <code>rx_buffer</code>.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The UART peripheral to configure </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">rx_buffer</td><td>The RX software buffer pointer </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">rx_buffer_size</td><td>The number of bytes in the RX software buffer </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the operation </dd></dl>

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